The present invention relates generally to integrated circuit testing techniques and, more particularly, to a technique for determining performance characteristics of electronic systems.
A typical transmission system comprises a transmitter, a receiver, and some form of transmission medium for carrying a signal from the transmitter to the receiver. A common problem that occurs in such a transmission system is that the signal arriving at the receiver may be distorted by Inter-Symbol Interference (ISI), or some other form of interference inflicted upon the signal. That is, the waveform (timing and voltage) of the signal transmitted by the transmitter may differ from the waveform of the signal received by the receiver. Most transmission systems are designed such that the system can accurately use the received signal to decipher, or as a representation of, the transmitted signal as long as the timing and voltage of the received signal are within the timing and voltage margins of the system.
ISI generally occurs due to two mechanisms. First, the timing or voltage of a signal presently being transmitted on any given transmission medium may be affected by residual reflections from prior transmitted signals on the same transmission medium. Second, adjacent transmission media may have electromagnetic coupling. In such a case, the timing or voltage of signals transmitted on a given transmission medium may be influenced by signals transmitted on other adjacent transmission mediums.
When testing transmission systems, the operation of such systems is often measured by transmitting long sequences of random data. To some degree, the accuracy of this approach depends upon the probability of the random data sequences containing a worst case data pattern (i.e., the data pattern is resulting in the greatest amount of distortion to a received signal). The accuracy of this approach is also dependent upon whether there is ISI or some other form of interference associated with the device or system. Further, the measurement apparatus may exhibit ISI or some other form of interference, thereby introducing an additional uncertainty. In some cases, guard-banding is employed to deal with these uncertainties.
Referring to FIG. 1, there is shown a typical apparatus for testing the operation of an integrated circuit (IC) memory device 12. The apparatus 10 comprises a vector memory 14 for storing random data sequences. The vector memory 14 is connected to a transmitter 16 for transmitting the random data sequences along a transmission medium 18 to the IC memory device 12. The apparatus 10 also comprises a receiver 20 for receiving data transmitted from the IC memory device 12 via the transmission medium 18, and a result memory 22, connected to the receiver 20, for storing the received data. The operation of the IC memory device 12 is tested by comparing the random data sequences that are transmitted from the vector memory 14 to the IC memory device 12 for storage therein with the same random data sequences after they are transmitted from the IC memory device 12 to the result memory 22 for storage therein. It should be noted that although only one transmitter 16, transmission medium 18, and receiver 20 are shown, this arrangement may be duplicated as required based upon the number of input/output (I/O) lines of the IC memory device 12 to be measured.
The apparatus 10 can also be used to attempt to measure the worst case timing and voltage margins of the IC memory device 12 by measuring the output waveforms of the random data sequences after they are transmitted from the IC memory device 12 to the result memory 22. However, since there is no way to know when a worst case data pattern will occur, every output waveform must be measured. Also, this method is not guaranteed to find the worst case timing and voltage margins since the random data sequences may not include the worst case data pattern. This is especially true when the outputs of the IC memory device 12 are affected by ISI or some other form of interference. In addition, if the apparatus 10 itself has ISI or some other form of interference, the measurement result will not accurately reflect the true worst case timing and voltage margins of the IC memory device 12.
In view of the foregoing, it would be desirable to provide a technique for determining performance characteristics of electronic systems which overcomes the above-described inadequacies and shortcomings.
According to the present invention, a technique for determining performance characteristics of electronic systems is provided. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.
In accordance with other aspects of this particular exemplary embodiment of the present invention, the method may also beneficially include the step of transmitting the worst case bit patterns from an electronic device onto the transmission medium for determining performance characteristics associated with the electronic device and the transmission medium. The performance characteristics may beneficially include worst case timing margins and/or worst case voltage margins associated with the electronic device and the transmission medium.
In accordance with further aspects of this particular exemplary embodiment of the present invention, the step of measuring a first response on a transmission medium may beneficially include the steps of sampling the voltage of the first response on the transmission medium, calculating the difference between each voltage sample and a steady state reference voltage, and generating a falling edge vector based upon the differences between each voltage sample and the steady state reference voltage. The voltage of the first response on the transmission medium may be periodically or non-periodically sampled.
In accordance with still further aspects of this particular exemplary embodiment of the present invention, the step of measuring a second response on a transmission medium may beneficially include the steps of sampling the voltage of the second response on the transmission medium, calculating the difference between each voltage sample and a steady state id reference voltage, and generating a rising edge vector based upon the differences between each voltage sample and the steady state reference voltage. The voltage of the second response on the transmission medium may be periodically or non-periodically sampled.
In accordance with additional aspects of this particular exemplary embodiment of the present invention, the step of determining worst case bit patterns may beneficially include determining worst case timing margin bit patterns and/or worst case voltage margin bit patterns for transmission on the transmission medium. For example, the step of determining worst case bit patterns may beneficially include the step of choosing a type of signal degradation parameter from a low side signal degradation, a high side signal degradation, a signal edge pull-in, or a signal edge push-off. The step of determining worst case bit patterns may also beneficially include the step of choosing an ending condition from a low output voltage level or a high output voltage level. The step of determining worst case bit patterns may also beneficially include the step of analyzing a falling edge vector generated based upon the first response or a rising edge vector generated based upon the second response to determine whether or not a state transition will cause a desired signal degradation at the ending condition. The step of determining worst case bit patterns may also beneficially include the step of analyzing the falling edge vector or the rising edge vector to determine whether or not a state transition will cause a desired signal degradation at each previously occurring bit time. This last step is beneficially. repeated using a desired amount of the falling edge vector and the rising edge vector.
In an alternative exemplary embodiment, the technique may be realized as an integrated circuit device having a transmitter for transmitting signals from the integrated circuit device onto a transmission medium. The integrated circuit device comprises a falling edge generator electrically connected to the transmitter for generating a falling edge signal for transmission by the transmitter onto the transmission medium so as to provide a falling edge response associated with the transmission medium for generating an associated falling edge vector. The integrated circuit device also comprises a rising edge generator electrically connected to the transmitter for generating a rising edge signal for transmission by the transmitter onto the transmission medium so as to provide a rising edge response associated with the transmission medium for generating an associated rising edge vector. In accordance with this particular exemplary embodiment of the present invention, if the falling edge generator and the rising edge generator may be formed in a combined falling/rising edge generator.
In another alternative exemplary embodiment, the technique may be realized as an integrated circuit device having a receiver for receiving signals from a transmission medium. The integrated circuit device comprises a sampling and differencing circuit electrically connected to the transmission medium for sampling a signal propagating along the transmission medium prior to being received by the receiver, and for calculating the difference between a sampled signal value and a reference value.
The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary, skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.